Here, an explanation is given in regard to the normally used access method for data of a semiconductor memory device.
In a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), ordinarily in the chip section, the memory elements are two-dimensionally arranged on a silicon flat surface. If one of the coordinates showing that two-dimensional arrangement is made the Xi address and the other the Yi address, a specific word line is first selected by means of the Xi address. As a result all of the memory elements connected to that word line are accessed at the same time by sense amplifiers of the same number as the memory elements. By means of the Yi address, only the desired data are selected from among that accessed data, then output. The time required for one series of operations--from the selection of a word line corresponding to this Xi address to the output of the sense amplifier of the data for the memory elements--is three times that required in the selection of the desired data corresponding to the succeeding Yi address.
Thus, in order to raise the data access efficiency in the DRAM, it is frequently the case that the Yi address selection mode (page mode) is made usable in which the operation is completed in a short time, in other words, a short cycle time. The page mode conducts the access of an Xi address in a fixed address sequence, to the extent possible without setting both the Xi address and the Yi address at each operating cycle as different values.
Also, in the DRAM, when viewed from the access operation for the data in which the Xi address is precharged at each change, a needless operation must be done; this is also linked to a lowering of the data access efficiency, but the number of times needless operation is performed can also be reduced using the page mode.
Also, there are instances in which an X-Y address applied to the chip from an external section and this Xi-Yi address corresponding to the memory element arrangement inside the chip do not match. Of course, the X-Y address and the Xi-Yi address correspond one-to-one, the input X-Y address is converted to a suitable Xi-Yi address, and a specific memory element is addressed.
As for the selection of the page in the above-mentioned page mode, ordinarily in order to conduct it by means of the X address, the X address is also called the page address. Also, in order to realize this page access operation without being in an unfavorable situation, the Xi address is set the same as the X address or a multiple integer of that.
However, if a page mode such as that mentioned above is only used normally, the data can be accessed quickly with good efficiency in the X address direction, but in the Y address direction the access of the data cannot be done at high speed and with good efficiency.
In order to solve this unsatisfactory problem, it is frequently the case that a method that remaps the data within one page to a two-dimensional plane surface is used.
For example, it is made 16 units of data within one page. It is expected that this is made a construction wherein a single data item within 16 units is selected by means of a 4-bit Y address, but this is not viewed as a space stipulated by an address of 4 bits, but is viewed as data of a space of, for example, 2 bits in the horizontal direction (H address) and 2 bits in the vertical direction (V address). In other words, as shown in FIG. 10, the 4.times.4 block is stored as the data for one page. If done in this manner, up to 4 data items can be accessed efficiently and with high-speed in both the H direction and the V direction.
With this method, the continuously accessible maximum length data number for one direction becomes [drops] from 16 to 4, and may be thought of as not increasing the efficiency, but actually it is frequently the case that the system efficiency is improved. For example, in the error correction for a DVD (Digital Video Disk), the data block is read out in the horizontal direction (PI) and the vertical direction (PO), and the process of error correction is executed in the respective directions, but this process is conducted in a parallel pipeline. Thus, if a large difference is created in the access time from the memory for the data in the horizontal direction and the vertical direction, a disorder is generated in the pipeline process; as a result, the system efficiency is lowered. However, if a remapping such as was mentioned above is conducted, since the readout can be done at the same speed for either the horizontal direction or the vertical direction, in such a system that conducts the parallel pipeline process, an improvement of the efficiency can be anticipated.
However, according to a method such as mentioned above, accessing of the data could be done with high efficiency in the X and Y directions, but in the diagonal direction of the X-Y address space, it was the case that the accessing of the data could not be done at high-speed with good efficiency.
As shown in FIG. 11, if it is the diagonal line (a) such as that beginning from the apex of the 4.times.4 block, the 4 units of data can be obtained based on a single page access in the same manner as the access of the data in the X and Y directions, but in the case in which it is offset from the apex of the 4.times.4 block, for example, of diagonal line (b), the data that can be obtained from a single block, in other words, the page access for one time, consists of only 2 units, and unless a page access for two times the number of the data access in the diagonal line (A) and the X and Y directions is performed, the diagonal line cannot be pursued.
Therefore, for example, in a case such as conducting the error correction for a CD-ROM (Compact Disk ROM), the data block is read out in the vertical direction and the diagonal direction (PO), and in the case of conducting a process such as executing the error correction in the respective directions, the data cannot be accessed with good efficiency at high-speed with a DRAM having a construction like those used until now.
Therefore, the objective of this invention is to offer a semiconductor memory device in which, when storing data having a two-dimensional construction, accessing of that stored data can be conducted at high speed in a diagonal direction.